The AT-LA500 USB PC Based Logic Analyzer provides an easy to use solution for real-time digital systems analysis, combining the advantages of a compact size instrument with the flexibility of your PC for data management and visualization, all at affordable price. AT-LA500 can be used as a single instrument with 36 Channels at 500 MS/s and a memory depth of up to 4 Million samples per channel.
With AT-XSS (Extended Synchronous System) expansion system you can also connect up to 8 AT-LA500s to expand the number of availables channels without loss of performance: 288 channels @ 500MS/s => Datasheet !

Connect your oscilloscope to AT-LA500 to make a unique
Mixed Signal Tester => Details.... !

AT-XSS permits also to connect other AT Test Equipment instruments (AWGs, Oscilloscopes,...) to create a complete measurement system.

Features

• 36 Channels @ 500MS/s
• Connect up to 8 instruments with AT-XSS bus
• 500 MHz Timing Analysis
• 200 MHz DDR / 100 MHz SDR State Analysis
• Up to 4 Million Samples on all channels
• Up to 130 min. of acquisition time
• Pattern and edge triggering
• 31 Trigger Levels
• 3 probe sets hot pluggable
• 4 programmable and independent thresholds on each instrument
• 4 Channels for External Clock
• 4 Independent programmable thresholds
• 1 Meter length probe
• Wide Voltage input range: -40V to 40V with Active HiZ Probe
• USB 2.0 interface (also supports USB 1.1)
• Windows 2000/XP OS

User friendly software permits to use advanced logic analyzer features without buttons, knobs and touch screen on the instrument; USB 2.0 interface transfers the acquired data to the PC within seconds => DEMO-Software !

GigaView

Nowadays digital devices have become more complex, more sensitive to signal quality and harder to debug including high-frequency buses and high speed logic families.

Debugging digital hardware can be a difficult and long operation because new effects caused by fast edges like logic errors, crosstalk, ground bounce and power distribution artifacts can occur.
Timing error debugging includes the characterization of the following problems:

• Glitches
• Setup/Hold Violations
• Timing Margin
• Verification
• Crosstalk/ Jitter Analysis

Thanks to the GigaView technology the AT-LA500 is capable of performing timing error debugging despite of general purpose logic analyzers that are traditionally unable to perform such kind of analysis. The GigaView technology provides a 2ns timing resolution with up to 4 MSamples depth simultaneously with a 666 ps high resolution timing within the same acquisition and using the same probes.

It is like performing two analysis in one: a deep timing analysis and an additional high-resolution timing analysis.

Glitches
are usually very narrow pulses that can be very difficult to detect, capture and hard to resolve.. Their effect are often unpredictable and they can be the first sign of device faults like driver errors, timing violations and crosstalk.

AT-LA500 deep timing signal waveform ( 2ns resolution and up to 4 MSamples memory depth) can examine all the signal lines of the bus at once and look for events or faults; after a particular event, like a glitch, has been detected, the GigaView waveforms can display all the channels in high resolution (666 ps) with 1024 samples depth per channel, providing the way to examine the event in detail.

GigaView high-resolution timing window is able to reveal glitches and to measure their duration with high accuracy.

Setup/Hold Violations
Setup/Hold parameter is a common source of digital system errors and its analysis can be difficult with the traditional approach of probing a clock and a data line using a oscilloscope.

The logic analyzer approach can monitor simultaneously every signal in the system for detecting setup/hold violations and when a problem is discovered in a particular time window, the AT-LA500 GigaView can measure in that window setup/hold times with an accuracy of 666 ps.

Timing Margin Verification
666 ps resolution on all channels with a maximum skew of 666 ps from channel to channel, allows designers to move from simply troubleshooting apparent problems to actually verifying the timing margins of their designs. Sample points can be moved in 666 ps increments to precisely determine setup-and-hold windows and examine the behavior of clocks, data and address lines with respect to each other, and asynchronous inputs.